1. Field
Embodiments of the present disclosure generally relate to the formation of a dielectric layer structure that includes an air gap structure using an integrated processing system.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The demand for greater circuit density necessitates a reduction in the dimensions of the integrated circuit components, e.g., sub-micron dimensions and the use of various materials to fabricate devices in order to achieve much faster and better electrical performance, such as materials with higher conductivity used to form metal lines, materials with lower permittivity (low-k) dielectric constant used as an insulating layer, etc. For integrated circuit fabrication, metal interconnects with low resistance, such as copper and aluminum interconnects, provide conductive paths between the integrated circuit components on integrated circuit devices. Generally, metal interconnects are electrically isolated from each other by a dielectric bulk insulating material. At sub-micron dimensions, capacitive coupling potentially occurs between adjacent metal interconnects, which may cause cross talk and/or resistance-capacitance (RC) delay and degrade the overall performance of the integrated circuit.
One method for forming vertical and horizontal interconnects for the integrated circuit components is by a damascene or dual damascene method. Typically, damascene structures have dielectric bulk insulating layers and conductive metal layers, such as low dielectric constant materials and conductive copper layers, stacked on top of one another. Vertical interconnects, i.e., vias, and horizontal interconnects, i.e., trenches are etched into the dielectric bulk insulating layer and the conductive metal layers are subsequently filled into the vias and/or trenches and planarized, such as by a chemical mechanical planarization process (CMP), so that the conducting metal materials are only left in the vias and/or trenches. In the damascene approach, a rather complex dielectric film stack that includes a sequence of hard mask, low-k dielectrics, etch stop layers, air gaps, etc., may be required. To obtain such a stack, via/trench lithography, patterning, and wet cleaning processes are typically required before filing the vias and the trenches with the conductive metal materials.
FIG. 1 depicts an integrated layer stack 100 fabricated by a conventional oxide or low-k material mold wet etching removal technique used to form at least part of an interconnect structure on a surface of a semiconductor substrate 101. The integrated layer stack 100 is fabricated by a blanket mold film (not shown) deposited over a low-k dielectric material disposed on the substrate 101. The mold film is patterned to selectively remove portions of the mold film layer to form a trench therein. A barrier layer 104 is deposited over the patterned low-k dielectric material 106, and a conductive material 102 is deposited in the trench over the barrier layer 104. The barrier layer 104 is configured to prevent diffusion between the conductive material 102 and the adjacent flowable low-k dielectric material 106. A chemical mechanical planarization process is then performed to polish back the mold oxide and the barrier layer 104 to expose a top surface of the conductive material 102. A wet etching technique removes the remaining mold film to form the integrated layer stack 100 shown in FIG. 1. Subsequently, an air gap structure 110 is formed between the first flowable low-k material 106 and a second flowable low-k material 108.
Conventional wet etching techniques, however, are problematic, because etchants used to remove the mold layer (not shown), such as hydrofluoric acid (HF) or dilute HF, may damage the barrier layer 104 as shown in region 112. Additionally, the wet etching may over-etch or attack the conductive material 102, as shown in region 114 where the conductive material 102 is recessed.
Additionally, long queue times at ambient conditions between the mold wet etching step and subsequent processes, such as air gap formation, may oxidize the barrier layer 104 and the conductive material 102. Therefore, there is a need for an improved interconnect formation process that does not etch or physically damage the conductive material 102 and barrier layer 104, and will further prevent the oxidation of the conductive material 102 and the barrier layer 104 during the formation process.